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74LV164 8-bit serial-in/parallel-out shift register
Product specification Supersedes data of 1997 Mar 28 IC24 Data Handbook 1998 May 07
Philips Semiconductors
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
FEATURES
* Wide operating voltage: 1.0 to 5.5V * Optimized for Low Voltage applications: 1.0 to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, * Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, * Gated serial data inputs * Asynchronous master reset * Output capability: standard * ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr =tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay CP to Qn MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per gate Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164. The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.
CONDITIONS CL = 15pF VCC = 3.3V
TYPICAL 12 12 78 3.5
UNIT ns MHz pF pF
VCC = 3.3V Notes 1 and 2
40
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV164 N 74LV164 D 74LV164 DB 74LV164 PW NORTH AMERICA 74LV164 N 74LV164 D 74LV164 DB 74LV164PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1
1998 May 07
2
853-1961 19349
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER 1,2 SYMBOL Dsa, Dsb Q0 to Q7 GND CP MR VCC Data inputs Outputs Ground (0V) Clock input (LOW-to-HIGH, edge-triggered) Master reset input (active LOW) Positive supply voltage FUNCTION
Dsa Dsb Q0 Q1 Q2 Q3 GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC Q7 Q6 Q5 Q4 MR CP
3, 4, 5, 6, 10, 11, 12, 13 7 8 9 14
LOGIC SYMBOL (IEEE/IEC)
SV00381
SRG8
LOGIC SYMBOL
8 9 R
C1/
1 Q0 1 Dsa Dsb 2 Q2 Q3 Q4 8 CP Q5 Q6 9 MR Q7 13 5 Q1 3 4 2
& 1D
3
4 5 6 6 10 10 11 11 12 13
12
SV00383
SV00382
1998 May 07
3
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
FUNCTIONAL DIAGRAM
FUNCTION TABLE
OPERATING MODES Reset (clear) INPUTS MR L H H H H CP X Dsa x l l h h Dsb x l h l h OUTPUTS Q0 L L L L H Q 1 - Q7 L-L q0 - q6 q0 - q6 q0 - q6 q0 - q6
Dsa 1 Dsb 2 8 9 CP MR 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
Shift
H h
Q0 3 Q1 4 Q2 5 Q3 6 Q4 10 Q5 11 Q6 12 Q7 13
L l q
= HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = Lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH clock transition
SV00384
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK IOK IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with -standard outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 50 -65 to +150 750 500 400 UNIT V mA mA mA mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note 1 MIN 1.0 0 0 -40 -40 - - - - - - - - TYP. 3.3 - - MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V C
tr, tf
ns/V
NOTES: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 May 07
4
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5V VCC = 1.2V VIL LOW level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5 VCC = 1.2V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage all outputs out uts voltage; VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VCC = 4.5V;VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; g STANDARD outputs VCC = 3.0V;VI = VIH or VIL; -IO = 6mA VCC = 4.5V;VI = VIH or VIL; -IO = 12mA VCC = 1.2V; VI = VIH or VIL; IO = 100A VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V;VI = VIH or VIL; IO = 100A VCC = 4.5V;VI = VIH or VIL; IO = 100A VOL LOW level output voltage; g STANDARD outputs Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0V;VI = VIH or VIL; IO = 6mA VCC = 4.5V;VI = VIH or VIL; IO = 12mA VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 1.0 160 850 A A A V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC V V MAX UNIT
VOL
LOW level output voltage out uts voltage; all outputs
II ICC ICC
NOTES: 1. All typical values are measured at Tamb = 25C.
1998 May 07
5
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay CP to Qn Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL Propagation delay MR to Qn Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Clock pulse width HIGH to LOW Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Master reset pulse width; LOW Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 trem Removal time MR to CP Figure 2 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tsu Set-up Set up time Dsa, Dsb to CP Figure 3 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 th Hold time Dsa, Dsb to CP Figure 3 2.7 3.0 to 3.6 4.5 to 5.5 2.0 fmax Maximum clock pulse frequency Figure 1 2.7 3.0 to 3.6 4.5 to 5.5 NOTE: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. MIN - - - - - - - - - - 34 25 20 13 34 25 20 13 - 19 14 11 8 - 22 16 13 9 - 5 5 5 5 14 19 24 36 LIMITS -40 to +85 C TYP1 75 26 19 142 122 75 26 19 142 122 9 6 52 42 10 8 62 52 30 10 8 62 52 15 5 4 32 22 -10 -3 -2 -22 -12 40 58 702 1002 - - - - - - - - - - - - - - - - - - MAX - 39 29 23 19 - 39 29 23 19 - - - LIMITS -40 to +125 C MIN - - - - - - - - - - 41 30 24 16 41 30 24 16 - 24 18 14 10 - 26 19 15 10 - 5 5 5 5 12 16 20 30 - - - MHz - - - - ns - - - - ns - - - - ns - - - ns MAX - 49 36 29 24 - 49 36 29 24 - - - ns ns ns UNIT
1998 May 07
6
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load.
Vl CP INPUT GND
t su t su
VM
th 1/fmax VI CP INPUT GND tw tPHL VOH Qn OUTPUT VOL VM tPLH VM VOH Vl
th
Dn INPUT GND
Qn OUTPUT VOL
Figure 3. Data set-up and hold times for the Dn inputs
SV00351
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency
TEST CIRCUIT
Vcc
Vi MR INPUT GND tw trem Vi CP INPUT GND tPHL VM VM
PULSE GENERATOR RT
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST VOH tPLH/tPHL Qn OUTPUT VOL VM
SV00352
Figure 2. The master reset (MR) pulse width, the master reset to output (Qn) propagation delay and the master reset to clock (CP) removal time
1998 May 07
7
IIIIIIII IIII IIIIIIII IIII IIIIIIII IIII
VM VM
SV00353
Vl D.U.T.
VO
50pF CL
RL= 1k
Test Circuit for Outputs
VCC < 2.7V 2.7-3.6V 4.5 V
VI VCC 2.7V VCC
SV00902
Figure 4. Load circuitry for switching times
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1998 May 07
8
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1998 May 07
9
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
1998 May 07
10
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
1998 May 07
11
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74LV164
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04431
Philips Semiconductors
1998 May 07 12

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